A. Technical Field
The present invention relates generally to network error detection and management devices, and more particularly, to network bit error rate testing.
B. Background of the Invention
The proliferation and significance of networking technology is well known. The ever-increasing demand for network bandwidth has resulted in the development of technology that increases the amount of data that can be pushed through a single channel on a network. Advancements in modulation techniques, coding algorithms and error correction have vastly increased the rates at which data travels across networks. For example, a few years ago, the highest rate that data could travel across a network was at about one Gigabit per second. This rate has increased ten-fold today where data travels across Ethernet and SONET networks at upwards of 10 Gigabits per second. Accurate error rate measurement during the development, manufacturing and installation of these networks is very important in order to ensure the integrity of data traveling across them once the network is in operation.
Traditionally, bit error rate testers have been used to determine an error rate along a particular path on a network. The bit error rate tester would transmit a bit sequence onto the network path and analyze the sequence when it returned. Typically, this analysis included the network. From this comparison, errors within the sequence were identified and counted resulting in a calculation of a bit error rate.
These traditional bit error rate testers were very limited as to the network paths that they could test. For example, if a network device inserted a fill word into the bit sequence (e.g., as part of a normal clock rate matching procedure), the transmitted and received bit sequences would not be synchronized and the bit error rate test could not meaningfully occur after the fill word was inserted. As a result, traditional bit error rate testers are limited to testing paths which do not insert or drop idles or fill words.
Accordingly it is desirable to provide a bit error rate tester that can compensate for modified idle or filler words surrounding a bit sequence. In particular, it is desirable to provide a bit error rate tester that can re-synchronize a received bit sequence and perform an error rate test on the sequence. Furthermore, it is desirable to provide such a bit error rate tester that is operable in today's high data rate networks.